Issue

Vol. 7 No. 2 (2015)

A Phase Change Memory Chip Based on TiSbTe Alloy in 40-nm Standard CMOS Technology

https://doi.org/10.1007/s40820-015-0030-z
Zhitang Song
State Key Laboratory of Functional Materials for Informatics, Shanghai Institute of Micro-system and Information Technology, Chinese Academy of Sciences, Shanghai 200050, People’s Republic of China
YiPeng Zhan
Semiconductor Manufacturing International Corporation, Shanghai 201203, People’s Republic of China
Daolin Cai
State Key Laboratory of Functional Materials for Informatics, Shanghai Institute of Micro-system and Information Technology, Chinese Academy of Sciences, Shanghai 200050, People’s Republic of China
Bo Liu
State Key Laboratory of Functional Materials for Informatics, Shanghai Institute of Micro-system and Information Technology, Chinese Academy of Sciences, Shanghai 200050, People’s Republic of China
Yifeng Chen
State Key Laboratory of Functional Materials for Informatics, Shanghai Institute of Micro-system and Information Technology, Chinese Academy of Sciences, Shanghai 200050, People’s Republic of China
Jiadong Ren
Semiconductor Manufacturing International Corporation, Shanghai 201203, People’s Republic of China

Corresponding Author: Daolin Cai

caidl@mail.sim.ac.cn

Nano-Micro Letters, Vol. 7 No. 2 (2015), Article Number: 172-176

Abstract

In this letter, a phase change random access memory (PCRAM) chip based on Ti0.4Sb2Te3 alloy material was fabricated in a 40-nm 4-metal level complementary metal-oxide semiconductor (CMOS) technology. The phase change resistor was then integrated after CMOS logic fabrication. The PCRAM was successfully embedded without changing any logic device and process, in which 1.1 V negative-channel metal-oxide semiconductor device was used as the memory cell selector. The currents and the time of SET and RESET operations were found to be 0.2 and 0.5 mA, 100 and 10 ns, respectively. The high speed performance of this chip may highlight the design advantages in many embedded applications.

Keywords

PCRAM Ti0.4Sb2Te3 alloy CMOS NMOS
Song, Zhitang, YiPeng Zhan, Daolin Cai, Bo Liu, Yifeng Chen, and Jiadong Ren. 2015. “A Phase Change Memory Chip Based on TiSbTe Alloy in 40-Nm Standard CMOS Technology”. Nano-Micro Letters 7 (2):172-76. https://doi.org/10.1007/s40820-015-0030-z.
Download Citation
Endnote/Zotero/Mendeley (RIS)
BibTeX
References
  1. A. Sebastian, M.L. Gallo, D. Krebs, Crystal growth within a phase change memory cell. Nat. Commun. 5, 4314 (2014). doi:10.1038/ncomms5314
  2. G. Burr, M. Breitwisch, M. Franceschini, D. Garetto, K. Gopalakrishnan, B. Jackson, B. Kurdi, C. Lam, L. Lastras, A. Padilla et al., Phase change memory technology. J. Vac. Sci. Technol. B 28(2), 223–262 (2010). doi:10.1116/1.3301579
  3. J. Liu, X. Xu, M.P. Anantram, Subthreshold electron transport properties of ultrascaled phase change memory. IEEE Electr. Device Lett. 35(5), 533–535 (2014). doi:10.1109/LED.2014.2311461
  4. D. Loke, T.H. Lee, W.J. Wang, L.P. Shi, R. Zhao, Y.C. Yeo, T.C. Chong, S.R. Elliott, Breaking the speed limits of phase-change memory. Science 336, 1566–1569 (2012). doi:10.1126/science.1221561
  5. F. Xiong, A.D. Liao, D. Estrada, E. Pop, Low-power switching of phase change materials with carbon nanotube electrodes. Science 332(6029), 568–570 (2011). doi:10.1126/science.1201938
  6. A.V. Kolobov, P. Fons, A.I. Frenkel, A.L. Ankudinov, J. Tominaga, T. Uruga, Understanding the phase-change mechanism of rewritable optical media. Nat. Mater. 3(10), 703–708 (2004). doi:10.1038/nmat1215
  7. Z.M. Sun, J. Zhou, R. Ahuja, Structure of phase change materials for data storage. Phys. Rev. Lett. 96(5), 055507 (2006). doi:10.1103/PhysRevLett.96.055507
  8. G.F. Close, U. Frey, J. Morrish, R. Jordan, S.C. Lewis, T. Maffitt, M.J. BrightSky, C. Hagleitner, C.H. Lam, E. Eleftheriou, A 256-Mcell phase-change memory chip operating at 2+ bit/cell. IEEE Trans. Circuits-I 60(6), 1521–1533 (2013). doi:10.1109/TCSI.2012.2220459
  9. K.J. Lee, B.H. Cho, W.Y. Cho, S. Kang, B.G. Choi, H.R. Oh, C.S. Lee, H.J. Kim, J.M. Park, Q. Wang et al., A 90 nm 1.8 V 512 Mb diode-switch pram with 266 Mb/s read throughput. IEEE J. Solid-State Circuits 43(1), 150–162 (2008). doi:10.1109/JSSC.2007.908001
  10. S. Gerardin, M. Bagatin, A. Paccagnella, A. Visconti, M. Bonanomi, S. Beltrami, V. Ferlet-Cavrois, Upsets in phase change memories due to high-LET heavy ions impinging at an angle. IEEE Trans. Nucl. Sci. 61(6), 3491–3496 (2014). doi:10.1109/TNS.2014.2367655
  11. G. Servalli, A 45 nm Generation Phase Change Memory Technology. International electron devices meeting, Maryland, USA (December 7–9, 2009): IEDM, pp 113–116 (2009). doi:10.1109/IEDM.2009.5424409
  12. P. Zhou, B. Zhao, J. Yang, Y. Zhang, Throughput enhancement for phase change memories. IEEE Trans. Comput. 63(8), 2080–2093 (2014). doi:10.1109/TC.2013.76
  13. M. Zhu, M.J. Xia, F. Rao, X.B. Li, L.C. Wu, X.L. Ji, S.L. Lv, Z.T. Song, S.L. Feng, H.B. Sun, S.B. Zhang, One order of magnitude faster phase change at reduced power in Ti–Sb–Te. Nat. Commun. 5, 4086 (2014). doi:10.1038/ncomms5086
  14. M. Zhu, L. Wu, F. Rao, Z. Song, K. Ren, X. Ji, S. Song, D. Yao, S. Feng, Uniform Ti-doped Sb2Te3 materials for high-speed phase change memory applications. Appl. Phys. Lett. 104(5), 053119 (2014). doi:10.1063/1.4863430
  15. F. Bedeschi, R. Fackenthal, C. Resta, E.M. Donzè, M. Jagasivamani, E.C. Buda, F. Pellizzer, D.W. Chow, A. Cabrini, G.M.A. Calvi et al., A bipolar-selected phase change memory featuring multi-level cell storage. IEEE J. Solid-State Circuits 44(1), 217–227 (2009). doi:10.1109/JSSC.2008.2006439
  16. S.H. Lee, H.C. Park, M.S. Kim, H.W. Kim, M.R. Choi, H.G. Lee, J.W. Seo, S.C. Kim, S.G. Kim, S.B. Hong, et al., Highly Productive PCRAM Technology Platform and Full Chip Operation: Based on 4F2 (84 nm Pitch) Cell Scheme for 1 Gb and Beyond. International Electron Devices Meeting, Washington, USA (December 5–7, 2011): IEDM, pp 47–50 (2011). doi:10.1109/IEDM.2011.6131480
  17. M.J. Kang, T.J. Park, Y.W. Kwon, D.H. Ahn, Y.S. Kang, H. Jeong, S.J. Ahn, Y.J. Song, B.C. Kim, S.W. Nam, et al., PRAM Cell Technology and Characterization in 20 nm Node Size. International Electron Devices Meeting, Washington, USA (December 5–7, 2011): IEDM, pp 39–42 (2011). doi:10.1109/IEDM.2011.6131478
  18. D.L. Cai, H.P. Chen, Q. Wang, Y.F. Chen, Z.T. Song, G.P. Wu, S.L. Feng, An 8 Mb phase change random access memory chip based on a resistor-on-via-stacked-plug storage cell. IEEE Electr. Device Lett. 33(9), 1270–1272 (2012). doi:10.1109/LED.2012.2204952
  19. G.D. Sandre, L. Bettini, A. Pirola, L. Marmonier, M. Pasotti, M. Borghi, P. Mattavelli, P. Zuliani, L. Scotti, G. Mastracchio, F. Bedeschi, R. Gastaldi, R. Bez, A 4 Mb LV MOS-selected embedded phase change memory in 90 nm standard CMOS technology. IEEE J. Solid-State Circuits 46(1), 52–63 (2011). doi:10.1109/JSSC.2010.2084491
  20. F. Bedeschi, R. Bez, C. Boffino, E. Bonizzoni, E.C. Buda, G. Casagrande, L. Costa, M. Ferraro, R. Gastaldi, O. Khouri, F. Ottogalli, F. Pellizzer, A. Pirovano, C. Resta, G. Torelli, M. Tosi, 4-Mb MOSFET-selected-trench phase-change memory experimental chip. IEEE J. Solid-State Circuits 40(7), 1557–1565 (2005). doi:10.1109/JSSC.2005.847531
  21. D. Kau, S. Tang, I.V. Karpov, R. Dodge, B. Klehn, J.A. Kalb, J. Strand, A. Diaz, N. Leung, J. Wu, et al., A Stackable Cross Point Phase Change Memory. International Electron Devices Meeting, Maryland, USA (December 7–9, 2009): IEDM, pp 617–620 (2009). doi:10.1109/IEDM.2009.5424263
Read More
Author biographies are not available.
Download this PDF file
PDF
Statistic
Read Counter : 1468 Download : 1115

Most read articles by the same author(s)