Recent Advances in In-Memory Computing: Exploring Memristor and Memtransistor Arrays with 2D Materials
Corresponding Author: Yong‑Wei Zhang
Nano-Micro Letters,
Vol. 16 (2024), Article Number: 121
Abstract
The conventional computing architecture faces substantial challenges, including high latency and energy consumption between memory and processing units. In response, in-memory computing has emerged as a promising alternative architecture, enabling computing operations within memory arrays to overcome these limitations. Memristive devices have gained significant attention as key components for in-memory computing due to their high-density arrays, rapid response times, and ability to emulate biological synapses. Among these devices, two-dimensional (2D) material-based memristor and memtransistor arrays have emerged as particularly promising candidates for next-generation in-memory computing, thanks to their exceptional performance driven by the unique properties of 2D materials, such as layered structures, mechanical flexibility, and the capability to form heterojunctions. This review delves into the state-of-the-art research on 2D material-based memristive arrays, encompassing critical aspects such as material selection, device performance metrics, array structures, and potential applications. Furthermore, it provides a comprehensive overview of the current challenges and limitations associated with these arrays, along with potential solutions. The primary objective of this review is to serve as a significant milestone in realizing next-generation in-memory computing utilizing 2D materials and bridge the gap from single-device characterization to array-level and system-level implementations of neuromorphic computing, leveraging the potential of 2D material-based memristive devices.
Highlights:
1 State-of-the-art research on two-dimensional material-based memristive arrays is comprehensively reviewed.
2 Critical steps in achieving in-memory computing are identified and highlighted, covering material selection, device performance analysis, and array structure design.
3 Challenges in progressing from single-device characterization to array-level and system-level implementations are discussed, along with proposed solutions.
Keywords
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